Logo ČVUT
ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2019/2020

Systems on Chip

Přihlášení do KOSu pro zápis předmětu Zobrazit rozvrh
Kód Zakončení Kredity Rozsah Jazyk výuky
MIE-SOC.16 Z,ZK 5 2P+1C
Přednášející:
Hana Kubátová (gar.)
Cvičící:
Hana Kubátová (gar.)
Předmět zajišťuje:
katedra číslicového návrhu
Anotace:

Students gain key knowledge and skills in the design of large-scale digital systems. They will be familiar with architectures of such systems and communication among their parts. They will use an appropriate workflow to design these architectures, their hardware and software. They will also have knowledge of contemporary methods of large systems verification and fault-tolerant systems design.

Požadavky:

Design and test of combinational and synchronous sequential digital circuits and corresponding workflows. System modeling and modeling languages. Basic overview of verification methods.

Osnova přednášek:

1. A taxonomy and characteristics of systems on a chip (SoC). Common requirements to SoC. Implementation platforms, granularity.

2. Communications on the chip, latency, throughput, architectures.

3. Hardware-software decomposition, design space exploration.

4. System-level timing, scheduling algorithms, time-triggered architectures.

5. Real-time operating systems and their architectures, implementation of synchronization primitives, communication interfaces.

6. Real-time applications, fault-tolerant software.

7. Hardware timing and synchronization, cycle-accurate models, model refinement.

8. Networks on chip (NoC), routing protocols and their implementation.

9. Design reuse, third-party intellectual property cores, standard communication and test interfaces.

10. SoC verification methods. Assertions, Property Specification Language, model checking.

11. Verification by simulation, simulation cover monitoring and control, random stimuli method.

12. Verification of protocols, state machines, interfaces, data paths. Equivalence checking. Software verification. Software-hardware coverification.

13. Large-scale fault-tolerant systems. Fault-tolerance methods for hardware and software.

Osnova cvičení:

1. Practical HW/SW Co-Design (Xilinx Zynq)

2. Practical HW/SW Co-Design - implementations

3. Processor design in CODASIP

5. Consultations and implementations

6. Semestral projects for Zynq

7. Project review and discussion

9. Consultation

10. Project review and discussion

11. Consultation

12. Project presentations, evaluation

13. Project presentations, evaluation

Cíle studia:

Modern highly integrated digital systems are designed to achieve high performance, small dimensions, and low energy consumption. The module brings knowledge required to design both the software and the hardware of such systems, because both areas are tightly coupled. Nevertheless, design is only a small part of the game. „We will die of verification“ was heard at conferences as early as in 2000, in reference to difficult verification of system correctness. Therefore, we present the contemporary state-of-the-art in this area, as it is necessary for verification engineers. The last part of the course is dedicated to the construction of dependable systems for critical applications.

Studijní materiály:

1. Pasricha, S., Dutt, N. ''On-Chip Communication Architectures: System on Chip Interconnect''. Morgan Kaufmann, 2008. ISBN 012373892X.

2. Erbas, G. ''System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures''. Amsterdam University Press, 2006. ISBN 9056294555.

Poznámka:

Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/MIE-SOC/

Rozsah: 2p+1c

Další informace:
https://courses.fit.cvut.cz/MIE-SOC/
Rozvrh na zimní semestr 2019/2020:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Po
Út
místnost TH:A-1048
Kubátová H.
11:00–12:30
(přednášková par. 1)
Thákurova 7 (FSv-budova A)
Servitova laborka
St
místnost TH:A-1048
Kubátová H.
11:00–12:30
SUDÝ TÝDEN

(přednášková par. 1
paralelka 101)

Thákurova 7 (FSv-budova A)
Servitova laborka
Čt

Rozvrh na letní semestr 2019/2020:
Rozvrh není připraven
Předmět je součástí následujících studijních plánů:
Platnost dat k 17. 9. 2019
Aktualizace výše uvedených informací naleznete na adrese http://bilakniha.cvut.cz/cs/predmet4660006.html