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ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2018/2019

Practical Digital Design

Předmět není vypsán Nerozvrhuje se
Kód Zakončení Kredity Rozsah Jazyk výuky
BIE-PNO KZ 5 2+2
Přednášející:
Cvičící:
Předmět zajišťuje:
katedra číslicového návrhu
Anotace:

Students get an overview of the contemporary digital design flow and learn practical skills to use synchronous design techniques. They understand the basics of the VHDL language, and implementation technologies FPGA and ASIC.

Požadavky:

Basic knowledge of architectures of computers and their units and of digital system design techniques.

Osnova přednášek:

1. Contemporary digital design flow.

2. Project management, metrics and estimates.

3. Fundamentals of synchronous design.

4. Digital circuits implementation technologies - ASICs, FPGAs.

5. Design at the algorithm level, decomposition to blocks.

6. VHDL language for description of digital circuits.

7. Circuit description on the RT level - registers, counters, multiplexers.

8. Circuit description on the RT level - arithmetics.

9. Circuit description on the RT level - on-chip memories.

10. Synthesis from RT level - the use of constraints.

11. Verification plan, models of verification.

12. Implementation of a testbench.

13. Design for testability.

Osnova cvičení:

1. Introduction to the subject.

2. [3] Introduction and exercises with FPGA EDA tool.

3. [3] Design and verification of a simple synchronous circuit.

4. [5] Individual work on the semestral project.

5. Presentation of the results.

Cíle studia:

The module is mostly targeted for practically oriented bachelor students, who would like to get acquainted with the current digital circuit design. The focus is on synchronous design policies, essentials of the VHDL language, and implementation technologies FPGA and ASIC. In the labs, students will get practical experience in the design of digital circuits using EDA tools for FPGAs and demonstrate their knowledge in a module project. A short visit in a professional design center is also envisaged.

Studijní materiály:

1. Ashenden, P. J. The designer's guide to VHDL, 3rd Edition. Morgan Kaufmann, 2008. ISBN 0120887851.

2. Smith, M. J. S. ''Application-Specific Integrated Circuits''. Addison-Wesley Professional, 1997. ISBN 0201500221.

3. Keating, M., Bricaud, P. ''Reuse Methodology Manual for System-on-a-Chip Designs''. Springer, 2007. ISBN 0387740988.

Poznámka:
Další informace:
Pro tento předmět se rozvrh nepřipravuje
Předmět je součástí následujících studijních plánů:
Platnost dat k 21. 4. 2019
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