Synthesis of Integrated Electronic Systems

The course is a substitute for:

Synthesis of Integrated Electronic Systems (X34SIE)

Lecturer:

Tutor:

Supervisor:

Department of Microelectronics

Synopsis:

Introduction to basic building blocks, architecture and design methodologies of advanced VLSI systems. Structure and design of digital and analogue integrated circuit subsystems. Integrated system description and synthesis using cell libraries and IP cores. Synchronization, power consumption and parasitics reduction issues. Testing and reliability of integrated systems. In seminars and labs, the hardware description language VHDL will be explained and used for practical design, synthesis and testing of a system on chip.

Requirements:

http://www.micro.feld.cvut.cz/home/X34SIE

Basic knowledge of digital circuit design, electronic and integrated structures.

Syllabus of lectures:

1. Integrated systems - historical outline. VLSI system design: principles, domains, and hierarchy.

2. Levels of system description. Hardware description languages. Basics of VHDL syntax.

3. VHDL language - entity, architecture, data types and objects, parallel and sequential domain for system description.

4. VHDL language - assignment statements for system description, state automata and models for verification.

5. VHDL language - hierarchy, parameterized models, libraries. System design in Verilog and SystemC.

6. Hardware platforms. Design approaches: full-custom, ASICs. Internal architecture a cell libraries.

7. Programmable systems: technologies, architectures, and applications.

8. Digital system design, synthesizable VHDL models (memories, PLA, adders and multipliers).

9. Macroblocks, IP cores and library cells. Behavioral synthesis, RTL model, algorithms and procedures.

10. Logical synthesis, methods and constraints, pipelining. Logical simulation, methods and procedures.

11. Testing and reliability. Fault models and localization. Test design and analysis.

12. Synthesis of topology. Floorplanning, power and datapath distribution.

13. Systems on chip (SoC) and reconfigurable systems.

14. Testability and methods of its improvement. Design and fabrication documentation.

Syllabus of tutorials:

1. Design system ISE: introduction into integrated system design - entry, synthesis, implementation.

2. Design system ISE: functional, logical and timing analysis. Digital system model in VHDL

3. VHLD - description of combinational (buffers, decoders, multiplexers) and sequential (counters) functions.

4. VHDL - hierarchical design and verification models (testbenches).

5. VHDL - state automata description and design of complex sequential systems.

6. State automata description in the StateCad environment, end of model project.

7. Migration of model design into different architectures, design reuse.

8. IP core libraries, design using IP core generators.

9. Floor planning and timing analysis, design of architecture specific blocks.

10. Description of course works, used IP modules, test.

11. Practical design of integrated system based on FPGA or SoC.

12. Practical design of integrated system based on FPGA or SoC.

13. Practical design of integrated system based on FPGA or SoC.

14. Presentation of course works, correction test, account.

Study Objective:

Understand principles and procedures of complex integrated systems design. Practical experience with design of system on chip using FPGA.

Study materials:

1. Wayne Wolf : ?Modern VLSI Design: System-on-Chip Design?, Prentice-Hall, 2002

2. Neil Weste,Kamran Eshraghian:?Principles of CMOS VLSI Design: A System Perspective?, Addison-Wesley, 2002

3. Michael J. S. Smith: ?Application-Specific Integrated Circuits?, Addison-Wesley, 2001

4. Pong P. Chu: ?RTL Hardware Design using VHDL?, Wiley-Interscience, 2006

Note:

Further information:

No time-table has been prepared for this course

The course is a part of the following study plans:

• Computer Science and Engineering (elective course)