Logical Simulation

Lecturer:

Tutor:

Supervisor:

Department of Computer Science and Engineering

Synopsis:

Digital circuit simulation: introduction, general principles of synchronous and asynchronous simulation, introduction to VHDL: entities and architectures, data types, variables, signals, behavioral description of the digital circuits : sequential statements and processes, concurrent statements and data-flow description, structural description of digital circuits, procedures, functions, resolved signals and resolved functions, packages, signal attributes, overloading, blocks and guarded blocks, configurations.

Requirements:

Syllabus of lectures:

1. General introduction to system simulation

2. General principles of digital circuits simulation

3. Synchronous models of digital circuits in universal languages

4. Principles of asynchronous simulation of digital circuits

5. Introduction to VHDL: entities and architectures

6. VHDL: data types survey, variables and signals

7. VHDL: functional description of digital circuits, processes

8. VHDL: parallel environment, data-flow description

9. VHDL: structural description of digital circuits, components

10. VHDL: data types attributes and signal attributes

11. VHDL: functions and procedures, resolved functions and signals

12. VHDL: libraries, overloaded functions and procedures

13. VHDL: models modification and structures configuration

14. Reserve

Syllabus of tutorials:

1. Basic concepts

2. Synchronous models of some MSI circuits in Pascal language

3. Synchronous model of microprocessor slice 2901 in Pascal

4. Basic principles of asynchronous models

5. Familiarization with VHDL simulation system

6. Entity declaration, styles of architecture description

7. Transport and inertial delay

8. Functional asynchronous models of typical SSI circuits.

9. Interfacing components in structural models

10. Structural asynchronous models of typical MSI circuits.

11. Functional model of cache memory controller

12. Functional model of traffic light controller

13. Modelling edge sensitive circuits

14. Reserve

Study Objective:

Study materials:

Lipsett, R.- Shaeffer, C. F.- Ussery, C.: VHDL: Hardware description and design. Boston, Kluwer Academic Publishers 1989.

Douglas, L. Perry: VHDL. New York, McGraw-Hill 1991.

IEEE Standard VHDL (Language reference manual). New York, IEEE Inc. 1988.

Note:

Further information:

No time-table has been prepared for this course

The course is a part of the following study plans: