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ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2011/2012

Logical Circuits

Předmět není vypsán Nerozvrhuje se
Kód Zakončení Kredity Rozsah Jazyk výuky
XE36LOB Z,ZK 5 2+2s
Předmět je náhradou za:
Logické obvody (X36LOB)
Přednášející:
Neurčen (gar.)
Cvičící:
Neurčen (gar.)
Předmět zajišťuje:
katedra počítačů
Anotace:

The aim of this course is to cover the basic properties of logical circuits and to acquaint the students with methods of their design. Digital circuits of small, medium and large scale integration (e.g. NANDs, NORs, multiplexors, ROMs, PLAs, etc.) are assumed as building elements for the logical circuit design.

Požadavky:

Active participation in lab courses is necessary. Requirements for the assessment: elaborating a semester work and getting the necessary number of points.

Requirements for the exam: getting the assessment and the necessary number of points.

http://lob.felk.cvut.cz/x36lob/start.php?page=welcome&lang=en

Osnova přednášek:

1)Introduction to logical circuits, physical properties of basic digital elements.

2)Combinational circuits; logical functions and their specification.

3)Methods for reduction of logical expressions (Boolean algebra, maps, Quine-Mc Cluskey.

4)Designing combinational circuits (using basic gates, multiplexors, decoders, ROMs, PLAs.

5)Static and dynamic hazards in combinational circuits.

6)Synchronous sequential circuits, standard structure, basic properties.

7)Types of finite automata, their specification and mutual transformation.

8)Reduction of the automaton state set .

9)Types of latches and flip-flops and their properties.

10)Synthesis of sequential circuits (using SSI, MSI and LSI circuits as building elements.

11)Asynchronous sequential circuits, fundamental automata, stable states.

12)Hazards in asynchronous sequential circuits, coding inner states.

13)Basic approaches to digital circuit simulation.

14)Basic properties of the simulation language VHDL.

Osnova cvičení:

1)Seminar: using Boolean algebra for logical function minimization.

2)Lab: ISE design system - getting started.

3)Seminar: Using maps and designing the combinational circuit.

4)Lab: ISE - demonstrating its usage for the implementation of the combinational circuit.

5)Seminar: more designs of combinational circuits; the homework assignment.

6)Lab: ISE: implementation of the homework.

7)Seminar: test 1, conclusion of the combinational circuit design.

8)Lab: Laboro design kit - implementing simple memory elements. Project assignment.

9)Seminar: Designing the automata.

10)Lab: ISE - implementation of the counter.

11)Seminar: test 2, conclusion of the automata design.

12)Lab: ISE - implementation of the simple code lock.

13)Seminar: Using medium and large scale integration circuits for the design.

14)Lab: Project evaluation. Assessment.

Cíle studia:
Studijní materiály:

1. Milos Ercegovac, Tomas Lang, Jaime H. Moreno: Introduction to Digital Systems,

John Wiley & Sons, Inc., New York 1999.

2. Gajski, D. D.: Principles of Digital Design. Prentice-Hall International, Inc. 1997

Poznámka:

Logical Circuits

Další informace:
Pro tento předmět se rozvrh nepřipravuje
Předmět je součástí následujících studijních plánů:
Platnost dat k 9. 7. 2012
Aktualizace výše uvedených informací naleznete na adrese http://bilakniha.cvut.cz/cs/predmet11856504.html